Design Verification Engineer, Security

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  
• Experience with object oriented programming, or equivalent practical experience.
  
• Experience verifying digital systems incorporating standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science.
  
• Experience creating and using verification components and environments in a standard verification methodology such as UVM.
  
• Experience with constrained-random verification techniques, System Verilog Assertions (SVA), and assertion-based verification.
  
• Experience with GLS, low-power DV, and support of SOC DV.
  
• Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
  
• Experience verifying RTL using Systemverilog.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan the verification of complex security IPs and Subsystem by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using System Verilog and UVM.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.