Low power Design Verification Engineer, Security

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  
• Experience with random verification techniques, System Verilog Assertions, and assertion-based verification.
  
• Experience with power-aware simulations at IP/Subsystem level.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
  
• Experience with ASIC standard interfaces and memory system architecture.
  
• Experience with performance verification of ASICs and ASIC components.
  
• Experience in verification of security blocks or crypto blocks.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan Low-power and power-aware verification of complex Security hardware IPs at IP and subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using System Verilog and UVM.
• Contribute to low power Design Verification methodology across the team.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.