Design Verification Engineer, Security, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  
• 3 years of experience creating and using verification components and environments in UVM.
  
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
  
• Experience with verification techniques (i.e., constrained-random simulation, formal property verification or static verification).
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  
• Experience in verification of security blocks or crypto blocks.
  
• Experience with performance verification of ASICs and ASIC components.
  
• Experience with ASIC standard interfaces and memory system architecture.
  
• Experience with power-aware simulations (e.g., low-power DV), GLS, and support of SoC DV.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  
• Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM) or formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
  
• Participate with architecture, design teams, silicon validation, and software teams in defining the overall verification strategy of our SoCs.