isecjobs.com

Sr ASIC Design Verification Engineer (NetSec)

Santa Clara, CA

USD 159K-258K (estimate) Senior-level Full Time

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Found 1d ago
Tasks
Perks/Benefits
Skills/Tech-stack

C constrained random testing | C plus plus | C# | Constrained random | Constrained random testing | Coverage closure | Emulation | Formal Property | Formal property verification | Formal verification | Functional Coverage | Perl | Property verification | Python | Random testing | Reference Model | Regression testing | Scoreboards | Silicon validation | System simulation | SystemVerilog | UVM | Unix Shell

Education

Bachelor of Science | Master of Science

Roles

ASIC Design Verification Engineer | Design Verification Engineer | Engineer | Verification Engineer

Regions

North America

Countries

United States

States

California, US

Cities

Santa Clara, California, US

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