Staff SOC Engineer (Physical Design)
Tasks
- Collaborate with global teams and resolve design challenges
- Execute synthesis place and route CTS STA physical verification EMIR and timing closure
- Improve design methodologies and mentor junior engineers
- Own and deliver RTL2GDSII physical design
- Utilize Synopsys EDA tools and develop automation scripts
Perks/Benefits
Skills/Tech-stack
Clock Tree | Clock Tree Synthesis | Design Compiler | EMIR analysis | Floorplanning | High Frequency | High-frequency design | IC Compiler | IC Compiler II | Low power | Low power design | Perl | Physical Verification | Place and route | Power design | PrimeTime | Python | RTL2GDSII | Static Timing | Static Timing Analysis | Synopsys Design Compiler | Synthesis | TCL | Timing Analysis | Timing optimization
Education
Roles
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