Senior Detection Subsystem Hardware Engineer
USD 145K-225K (estimate) Senior-level Full Time
Tasks
- Author roadmap proposals
- Build hardware in the loop test rigs
- Build verification and validation strategy
- Conduct defect tracking and root cause analysis
- Create automated test frameworks
- Define detection technology roadmap
- Design end to end PIR subsystem
- Design sensor signal conditioning circuits
- Develop on device AI pipeline
- Integrate AI inference hardware
- Mentor engineers on best practices
- Optimize test yield
- Own detection subsystem architecture
- Perform field validation protocols
- Research and prototype emerging technologies
- Select and qualify PIR sensors
- Support manufacturing with test fixtures
- Tune signal processing pipelines
Perks/Benefits
- N/A
Skills/Tech-stack
Analog front end | Artificial Intelligence | Automated testing | BGT | C# | C++ | Computer Vision | Design review | Edge inference | EfficientDet | Embedded Systems | FreeRTOS | Front-end | Hardware-in-the-loop | Low power | Low power design | Machine Learning | MmWave | MobileNet | Model Quantization | ONNX | PCB design | PCB design review | PIR | Power design | RTOS | Radar Sensors | Schematic review | Signal Processing | TI mmWave | TensorFlow Lite | The Loop | Verification and Validation | YOLO | Zephyr
Education
Bachelor of Engineering | Bachelor of Science | Master of Science | PhD
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